Synthesizable model of Atmel ATmega103 microcontroller.

For the moment the model consists of the following blocks:
1. Atmel AVR core.
2. Program memory.
3. Data memory.
4. UART.
5. Timer/Counter.
6. PORTA.
7. PORTB.

                                    Limitations.
Core limitations : 
For the moment the core doesn’t support SLEEP and CLRWDT instructions.
  
UART limitations :
No (I hope!).

Timer/Counter limitations:
For the moment only Timer/Counter0 is implemented.
It emulates the asynchronous mode (The Timer/Counter0 of  Atmega103 microcontroller operates with two separate 
clock sources ).
Timer/Counter0 supports toggling of OC0/PWM0 output line , but doesn’t support set/reset of  this line.

PORTA and PORTB limitations:
PORTA and PORTB operate as parallel ports only and don’t support additional functions (OCx/PWMx , #INTx, etc.).

Additional features.
A simple timer was added to the model for the sake of test only.
It generates interrupt request(INT0) every 256 cycles of cp2. 

                                             Brief description of project structure.

test_avr_core2.vhd  - top level design (for simulation only)

AVR core:
avr_core.vhd                     - top level design of AVR core.
alu_avr.vhd                       - ALU 
bit_processor.vhd             - some bit operations
reg_file.vhd                      - register file
pm_fetch_dec.vhd            - main part of the core (instruction decoder, memory interfaces, etc. )
io_reg_file.vhd                 - I/O registers implemented inside the core(SREG, RAMP, SPH, SPL)
io_adr_dec.vhd                 - address decoder and data bus multiplexer for the I/O registers implemented inside the core

Microcontroller:
top_avr_core.vhd             - top level design  of  microcontroller
mux_type_package.vhd   - some constants and types
external_mux.vhd            - data bus multiplexer 
prom.vhd                          - program memory
ram.vhd                            - data RAM
portx.vhd                          -  parallel ports (PORTA,PORTB)
Timer_Counter.vhd          - Timer/Counter
uart.vhd                            - UART
simple_timer.vhd             - simple timer
Service_Module.vhd        - some additional control registers (MCUCR, MCUSR, XDIV, EIMSK, EIFR, EICR)
cpuwait.vhd                      - was added for the purpose of test only 

How to convert generic/hex file to VHDL source (for program memory).
GNR2VHD.EXE  converts generic file (.gnr extension )  to VHDL source file (prom.vhd).
HEX2VHD.EXE  converts generic file (.hex extension )  to VHDL source file (prom.vhd).

For the moment HEX2VHD.EXE doesn’t  support Intel-extended format.

Examples:
GNR2VHD your_genric_file.gnr
HEX2VHD your_hex_file.hex

Current status.
The core was tested with several C and ASM programs.
UART and Timer/Counter were  tested only once.

If you find a bug in this project, do  not  hesitate  to  report the problem to me
through e-mail  lepetenokr@yahoo.com

21.01.2002